| EPSRC Reference: |
GR/L35973/01 |
| Title: |
A HARDWARE COMPILATION WORKBENCH |
| Principal Investigator: |
Page, Dr I |
| Other Investigators: |
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| Researcher Co-Investigators: |
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| Project Partners: |
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| Department: |
Computer Science |
| Organisation: |
University of Oxford |
| Scheme: |
Standard Research (Pre-FEC) |
| Starts: |
01 July 1997 |
Ends: |
30 June 2000 |
Value (£): |
71,712
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| EPSRC Research Topic Classifications: |
| Parallel Computing |
System on Chip |
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| EPSRC Industrial Sector Classifications: |
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| Panel History: |
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Summary on Grant Application Form |
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To create a workbench to assist in the development of hardware transformation/compilation systems. This will support the rapid prototyping of such systems, as well as flexible experimentation with them. The needs of Handel system at Oxford will drive and focus the research. The project will draw on the distinctive expertise of the Automated Reasoning Group at the University of Cambridge in the areas of theorem prover design, semantic embedding and hardware verification and of the Hardware compilation group at Oxford University in the area of hardware compilation.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.ox.ac.uk |