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Details of Grant 

EPSRC Reference: GR/L28159/01
Title: RELIABILITY DESIGN FOR ULTRA-SHORT GATE CMOS TECHNOLOGIES
Principal Investigator: Taylor, Professor S
Other Investigators:
Marsland, Dr J
Researcher Co-Investigators:
Project Partners:
Pre Nexus Migration
Department: Electrical Engineering and Electronics
Organisation: University of Liverpool
Scheme: Standard Research (Pre-FEC)
Starts: 09 June 1997 Ends: 08 June 2000 Value (£): 126,292
EPSRC Research Topic Classifications:
VLSI Design
EPSRC Industrial Sector Classifications:
Electronics
Related Grants:
Panel History:  
Summary on Grant Application Form
The silicon MOSFET is the basic 'building block' of the majority of integrated circuits, including VLSI memory chips and ASICs. The operating characteristics of a MOSFET deteriorate during its lifetime, dependent on the electrical stress experienced. Eventually the MOSFET ceases to operate within its intended specification; this behaviour, repeated in even a small fraction of a FETs in a chip, can lead to unreliability or complete failure. In short-gate devices (which offer higher speeds and integration densities) the electrical stresses are greater, leading to accelerated degradation. Progress to ultra-small feature sizes (0.1 micron and less) in CMOS will be dependent on the ability of 'design out' degradation at the device level.The aims of this project are, by a combination of advanced theoretical and experimental techniques, to gain a detailed understanding of the physical mechanisms of hot electron-induced degradation of ultra-short-gate devices. This understanding will then be used to develop an accurate ageing simulator for VLSI OMOS design. Alternative FET gate dielectric materials will also be investigated in the quest for improved device reliability.
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Organisation Website: http://www.liv.ac.uk