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Details of Grant 

EPSRC Reference: GR/K75101/01
Title: MANUFACTURING DISCIPLINE FOR MULTILAYER SEMICONDUCTOR DEVICES
Principal Investigator: Kelly, Emeritus Professor MJ
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Zarlink
Department: Physics
Organisation: University of Surrey
Scheme: Standard Research (Pre-FEC)
Starts: 30 October 1996 Ends: 27 February 1999 Value (£): 180,025
EPSRC Research Topic Classifications:
Materials Processing
EPSRC Industrial Sector Classifications:
Electronics
Related Grants:
Panel History:  
Summary on Grant Application Form
We propose to advance the heterojunction Gunn diode from its present proof-of-principle state through to an engineered device capable of routine manufacture. We address the two key ingredients that are required. (1) A user-friendly device simulator is to be developed that can be used both (i) for designing multilayer structures (including the tolerances on each layer) and (ii) for reverse engineering to help ascertain any deviations of grown layers from specification and to refine layer specifications for improved performance. (2) A closed loop is to be established between design, growth and layer assessment: in particular, we must be able to determine precisely what layers have been grown, so that any deviations from specification can be used to relate to differences between designed and achieved dc and rf device performances. This work is being done in collaboration with GEC Plessey Semiconductors who have identified the automotive radar market as a target for exploiting the success of this project.
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Organisation Website: http://www.surrey.ac.uk