| EPSRC Reference: |
GR/K70175/01 |
| Title: |
HAZARD-FREE ARBITER DESIGN (HADES) |
| Principal Investigator: |
Yakovlev, Professor A |
| Other Investigators: |
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| Department: |
Computing Sciences |
| Organisation: |
Newcastle University |
| Scheme: |
Standard Research (Pre-FEC) |
| Starts: |
01 November 1996 |
Ends: |
29 February 2000 |
Value (£): |
129,046
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Summary on Grant Application Form |
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The project addresses the problem of designing reliable hardware support for the implementation of arbitration, synchronisation and resource allocation mechanisms employed in parallel and distributed system, as well as in modern, pipelined, microprocessors. Such mechanisms are essentially asynchronous and partly analogue, which requires developing new techniques and software tools for their modelling, functional and temporal verification and testing , and implementation by asynchronous VLSI circuits. Work also involves theoretical investigation of functional completeness of a logical gate library enhanced with standard metastability resolution devices. We plan to design and analyse a number of test examples: cascaded multi-way arbitration, distributed mutual exclusion protocols with priorities, multi-thread pipeline synchronisation. Work will complement and exploit the results of current EPSRC-project on methods and tools for asynchronous controllers.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.ncl.ac.uk |