EPSRC Reference: |
GR/J76927/01 |
Title: |
DATA OPTIMISATION TEST TECHNIQUES APPLIED TO EMBEDDED NON-LINEAR MACROS |
Principal Investigator: |
Raczkowycz, Dr J |
Other Investigators: |
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Researcher Co-Investigators: |
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Project Partners: |
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Department: |
Sch of Computing and Engineering |
Organisation: |
University of Huddersfield |
Scheme: |
Standard Research (Pre-FEC) |
Starts: |
01 February 1994 |
Ends: |
30 June 1996 |
Value (£): |
62,003
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EPSRC Research Topic Classifications: |
Design & Testing Technology |
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EPSRC Industrial Sector Classifications: |
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Related Grants: |
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Panel History: |
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Summary on Grant Application Form |
To extend previous work on complex embedded ADC test techniques to a range of ADC devices. Investigate the possibility of applying these techniques to sigma-delta converters with a view to using an embedded sigma-delta modulator as an on-chip testability macro. Progress:An embedded ADC may be used to test embedded analogue macros via defined scanpaths, where the predictability of these ADCs in terms of performance is an extremely important factor. A novel data analysis technique which characterises embedded ADCs has been developed. This technique alleviates scan-path loading and reduces the amount of primary-test data and computer-time intensive operations to a minimum. Using these techniques an 8 bit ADC has been characterised using 20% less data points than conventional techniques. Validation hardware has been designed and tests on practical ADCs initiated. The effects of ADC production tolerances has also been investigated. Work has commenced to broaden the application capabilities of data-optimisation by investigating the feasibility of using a sigma-delta modulator as a universal testability macro.
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Key Findings |
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Potential use in non-academic contexts |
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Impacts |
Description |
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Summary |
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Date Materialised |
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Sectors submitted by the Researcher |
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Project URL: |
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Further Information: |
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Organisation Website: |
http://www.hud.ac.uk |