Details of Grant 

EPSRC Reference:	GR/J45435/01
Title:	NOVEL TRANSPORT PHENOMENA IN SILICON STRUCTURES
Principal Investigator:	Broers, Lord A
Other Investigators:
Researcher Co-Investigators:
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Department:	Engineering
Organisation:	University of Cambridge
Scheme:	Standard Research (Pre-FEC)
Starts:	01 March 1994	Ends:	28 February 1997	Value (£):	217,076
EPSRC Research Topic Classifications:	Electronic Devices & Subsys. Materials Processing
EPSRC Industrial Sector Classifications:
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Panel History:
Summary on Grant Application Form
The objectives for our collaborative part of the efforts are:(i) to fabricate advanced silicon devices with reduced critical dimensions by using electron beam lithography(ii) to investigate and develop process techniques which will allow the structures to be fabricated with smaller dimensionsProgress:The initial devices processed were made from d-doped material grown at Warwick University and processed at Cambridge University (Physics) using Liverpool University low temperature oxide. Measurement conducted at CU(Physics) showed the resistivity of the devices at 4.2K too high so a second set of devices is currently being fabricated based on conventional MOSFET design. CU(Engineering) is presently fabricating single narrow line gates on these devices for testing at CU(Physics).In order to apply the direct-write SiO2 patterning techniques developed at CU(Engineering) to these structures, it was first necessary to characterise the Liverpool oxide. This unique, low temperature grown oxide was characterised in a series of exposure tests and found to be of high quality, and even slightly more sensitive to the gate fabrication process than typical thermal oxides. In addition to the device fabrication, we are also investigating the temperature effects of electron-beam direct write SiO2 process. There is evidence to suggest that it may be possible, by varying the etch temperature, to increase the sensitivity of the process. This investigation, which has only just begun, has the aim of achieving even better control of the gate oxide patterning of the devices being fabricated. Collaborators:Dr. Whall, Warwick University,Grant Reference No. GR/J49600Professor Pepper, Cambridge University,Grant Reference No. GR/J46357Professor Eccleston, Liverpool University,Grant Reference No. GR/J78211
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