Details of Grant 

EPSRC Reference:	GR/H82761/01
Title:	ALL DIGITAL MULTICARRIER DEMODULATOR ARRAY FOR ON-BOARD PROCESSING SATELLITES
Principal Investigator:	Evans, Professor B
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Department:	Satellite Engineering Research
Organisation:	University of Surrey
Scheme:	Standard Research (Pre-FEC)
Starts:	01 January 1993	Ends:	30 September 1996	Value (£):	123,149
EPSRC Research Topic Classifications:	Energy Efficiency RF & Microwave Technology
EPSRC Industrial Sector Classifications:	No relevance to Underpinning Sectors
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Panel History:
Summary on Grant Application Form
One of the key aspects of satellite on-board processing schemes is the demodulation of received signals to baseband. FDMA schemes appear most attractive for mobile applications which require that the satellite demodulate a large number of independent channels using a multicarrier demultiplexer and demodulator (MCD). The research is to reduce the complexity of MCDs by investigating alternative integration approaches of the three components: frequency DEMUX, sampling rate converter and demodulator, and to research into the feasibility of ASIC implementation of MCD.Progress:It has been shown that the structured multirate DSP approach is universally applicable to optimisation of multirate DSP systems (1). A full architecture & decomposition study of the MCD has been performed with conventional signal flow graph transforms. As a complement to these conventional design approaches, we have developed a multirate filter bank design approach based on the multirate flow graph (MFG) representation for multirate systems, which renders a direct & clearer link to the hardware structure and the parallelism of the filter bank than does the pure mathematical representation. Being an extension from the conventional signal flow graph, the MFG preserves most of its properties. In the multirate environment, properties & transformations of MFG are identified and defined. Starting from the mathematical definition of MCD under consideration, its multirate DSP model is transformed and simplified to a computational efficient MFG network using MFGs identities & transforms. Another advantage of MFG design approach is that the tradeoffs of VLSI complexity, power consumption & processing throughput can also be handled during the process of MFG network transformation. In order for MCD ASICs to achieve mass/volume and power efficiency, the mapping between multirate DSP structure & VLSI architecture has been studied. We have proposed a mapping method which determines the configuration of the arithmetic elements (adder, multiplier, etc) by choosing either bit-serial or bit-parallel architecture based on a multirate VLSI model, thus reducing the mapping problem to a constrained optimisation problem. The outcome of this approach is an optimal VLSI architecture for the given multirate system structure, subject to the particular constraints on VLSI complexity, power consumption & throughput. The proposed multirate VLSI model is useful in carrying out comparative study between different MCD architectures though the actual estimates complexity & power consumption may still be too coarse from VLSI engineering point of view. We have also investigated sampling schemes for MCD input (FDM) signals. An alternative to the conventional sampling approach, which involves down conversion of FDM signals at IF band to lower frequency band close to dc before A/D convert, is to sample FDM signals directly at IF bands according to classical first order bandpass sampling theorem. However, the minimum sampling rates given by the theorem are hardly attainable due to the requirement for infinite precision of sampling frequency & carrier frequency. We derived a set of formula to determine minimum sampling rates for given precision of sampling parameters & identified conditions at which tolerance to sampling process imperfection is maximised (eg. sampling of 1/4 or 3/4 stacking of bandpass signal - with respect to sampling frequency - is shown to be the least sensitive to centre frequency uncertainty implying high tolerance to Doppler effects).(1) above: W.H. Yim & F.P. Coakley, Polyphase Matrix & Lattice Decomposition for Multi-rate Filters & Filter Banks; Proc. IEEE International Conference on Acoustic, Speech & Signal Processing, ICASSP-92, Vol.4, pp. 625-627, March 1992.
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