Details of Grant 

EPSRC Reference:	EP/X039943/1
Title:	UKRI-RCN: Exploiting the dynamics of self-timed machine learning hardware (ESTEEM)
Principal Investigator:	Yakovlev, Professor A
Other Investigators:	Balsamo, Dr D Shafik, Professor R Granmo, Professor O
Researcher Co-Investigators:
Project Partners:	Cambridge Future Tech Ltd Pragmatic Semiconductor Limited
Department:	Sch of Engineering
Organisation:	Newcastle University
Scheme:	Standard Research
Starts:	01 November 2023	Ends:	30 April 2027	Value (£):	836,689
EPSRC Research Topic Classifications:	Artificial Intelligence Electronic Devices & Subsys. Fundamentals of Computing
EPSRC Industrial Sector Classifications:	Electronics Information Technologies
Related Grants:
Panel History:	Panel Date Panel Name Outcome 24 Apr 2023 EPSRC ICT Prioritisation Panel April 2023 Announced
Summary on Grant Application Form
People can often see these days adverts on media company vans like "Grab your life by the Gigabits" (Virgin Media). Similar slogans appear on IT company flyers offering data analysis at Tera operations per second. They show the undeniable progress in technology, though still rarely we see performance growth per energy, for example Gigabits per Joule. And yet we are increasingly having to face with rising energy bills. As appetites for extending our intelligence wider and deeper into our everyday life steadily grow the grand challenge of ICT in making intelligence energy efficient becomes more and more evident. A significant role in this belongs to the research that aims at finding better methods for machine learning and data classification where both power and time for performing key operations in learning are reduced. In simple terms reducing power amounts to reducing average switching activity of electronic hardware, while reducing time means determining the moments when the learning actions have reached the state of sufficient quality. Self-time hardware, which works on the event-driven principles, in combination with novel machine learning methods, based on efficient approximation and Boolean logic as opposed to heavy arithmetic, gives this research a lever of innovation and potential impact against the state of the art. This project will investigate opportunities for improving performance and energy efficiency in artificial intelligence hardware created by the inherent time and power elasticity of self-timed circuits. The project will lay foundation to a new design methodology for building electronic devices and systems with machine learning (ML) capabilities at the micro- and nano-scale granularity. Those devices will be widely leveraged in many at-the-edge applications such as environmental sensors, traffic monitors, wearables, as well potential commodity ML-enhanced devices that can be used as building blocks in computer systems of the future. Micro- and nanoclassifiers and decision makers that can operate in real-time with power/energy efficiency are expected to find many 'light-weight' applications, so optimal (in terms of latency and energy) control is crucial. Here is an example of handwritten character recognition by an electronic pen with energy-harvested power. A reference class is given (e.g., digit "5"). Then, a few attempts in handwriting of digit 5 are made. During all these attempts training is performed. Then another reference class is given, and similar training is performed on it, and so on. The key requirements are to keep time spent limited and consumed energy minimised. Training is to be done to the best of the achievable accuracy. There are several trade-offs involved between speed and power and accuracy of learning. The success of the project will be measured in terms of the answers to the key research questions about the dynamics of machine learning in self-timed circuits; for example, whether the asynchronous design approach combined with the use of learning automata and logic-based inference will reach minimum energy point for a given machine learning problem. The project outcomes in theory and design methodology will be validated by means of extensive simulations, prototyping, IC fabrication and testing, and, ultimately, via an embodiment of the new hardware solutions into a concrete IoT application. A particularly challenging and breaking through validation will be the development and fabrication of the first asynchronous machine learning integrated circuit using flexible substrates. The practical impact of this research will be in the directions and methods of designing intelligent embedded electronics that will be capable of performing run-time classification of data obtained from environmental sensors, audio and image signals, as well as fast moving consumer goods (FMCG) and smart packaging using flexible IC technology.
Key Findings
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Potential use in non-academic contexts
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Organisation Website:	http://www.ncl.ac.uk