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Details of Grant 

EPSRC Reference: EP/W003759/1
Title: Nervous Systems
Principal Investigator: Trefzer, Dr M A
Other Investigators:
Tyrrell, Professor A
Researcher Co-Investigators:
Project Partners:
Advanced Micro Devices Inc (AMD) ARM Ltd Thales Ltd
Department: Electronics
Organisation: University of York
Scheme: Standard Research
Starts: 01 January 2022 Ends: 31 December 2025 Value (£): 859,395
EPSRC Research Topic Classifications:
Electronic Devices & Subsys. Fundamentals of Computing
EPSRC Industrial Sector Classifications:
Electronics Information Technologies
Related Grants:
EP/W003783/1
Panel History:
Panel DatePanel NameOutcome
13 Sep 2021 EPSRC ICT Prioritisation Panel September 2021 Announced
Summary on Grant Application Form
Technology scaling has enabled fast advancement of computing architectures through high-density integration of components and cores, and the provision of systems on chip (SoC), e.g. NVIDIA Jetson, Xilinx UltraScale+ FPGA, ARM big.LITTLE.

However, such systems are becoming hot and more prone to failure and timing violations as clock speed limits are reached. Therefore, parts of SoCs must be turned off to stay within thermal limits ("dark silicon"). This shifts challenges away from making designs smaller, setting the new focus on systems that are ultra-low power, resilient and autonomous in their adaptation to anomalies, faults, timing violations and performance degradation. There is a significant increase in numbers of temporary faults caused by radiation, and permanent faults due to manufacturing defects and stress. ITRS (https://irds.ieee.org/) estimates significant device failure rates, e.g. due to wear-out, in the short term. Hence, a critical requirement for such systems is to effectively perform detection and analysis at runtime, within a minimal area and power overhead. This is at odds with current state-of-the-art, including error correcting codes (ECC), built-in-self-test (BIST), localized fault detection, and traditional modular redundancy strategies (TMR), all resulting in prohibitively high system overheads and an inability to adapt, locate or predict faults.

In complex living organisms, the nervous system is a much more efficient and adaptive "subsystem" that detects environmental changes and anomalies that impact them by transmitting signals between different parts of the organism. The nervous system works in tandem with the endocrine system, triggering appropriate regulatory or repair responses. Nervous systems naturally scale up, adapt and operate autonomously in a de-centralised manner. In NERVOUS our vision is to rejuvenate modern electronic systems and particularly the way in which such systems are designed to act autonomously to become more reliable.

The goal of NERVOUS is to develop a methodology for "self-aware" electronic systems with an embedded artificial nervous system that can sense its state and performance, and exploit the structure and computational power of these kinds of bio-inspired mechanisms for autonomous tolerance of faults. NERVOUS is an inter-disciplinary collaboration that brings together networks of spiking neurons with electronic systems, so that they form hardware platforms with inherently embedded artificial "nervous systems". This approach has never before been used to make the technology we all carry around in our pockets more efficient and reliable, making NERVOUS "blue-skies" research at the cutting edge of bio-inspired electronic systems design.

To ensure feasibility, NERVOUS's research programme is built around a number of hardware demonstrators of increasing complexity. NERVOUS is making use of state-of-the-art UltraScale+ FPGAs for rapid prototyping of nervous system components and complementing with an electronic design environment.

To ensure accessibility beyond the project, NERVOUS will develop a design methodology and an EDA tool supporting automatic integration and training of NERVOUS components with traditional circuit designs, allowing engineers to apply our technology without having to worry about the intricate details of electronic-neuron interfacing. NERVOUS will demonstrate this for digital FPGA designs at the HDL level in collaboration with Xilinx.

To ensure scalability, we will verify and evaluate the NERVOUS methodology on a range of relevant large-scale processor designs provided by our partner ARM, who will also advise on fault performance requirements.

To ensure a route to industrial application and exploitation, we will demonstrate the NERVOUS methodology in the context of a real-word space application, e.g. space networking IP and modular spacecraft controller, through collaboration and secondments with our project partner TAS-UK.
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Organisation Website: http://www.york.ac.uk