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Details of Grant 

EPSRC Reference: EP/V004859/1
Title: Zero-change manufacturing of photonic interconnects for silicon electronics
Principal Investigator: Strain, Dr MJ
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Alter Technology TUV Nord Fraunhofer Institut (Multiple, Grouped) Stanford University
Department: Inst of Photonics
Organisation: University of Strathclyde
Scheme: Standard Research
Starts: 01 July 2021 Ends: 31 December 2024 Value (£): 509,739
EPSRC Research Topic Classifications:
Optoelect. Devices & Circuits
EPSRC Industrial Sector Classifications:
Information Technologies
Related Grants:
EP/V005022/1
Panel History:
Panel DatePanel NameOutcome
03 Aug 2020 EPSRC ICT Prioritisation Panel August 2020 Announced
Summary on Grant Application Form
The silicon electronics industry has two major challenges in the development of new products: demand for increasing levels of processing power on a single chip and the amount of energy required to run these chips. The two challenges are linked, since the more components and communications links that are integrated into the chip, the higher the associated energy usage. While the energy consumption of a single chip is relatively low, this rapidly scales to environmental levels when considering the huge volume of units produced each year is in the order of 10's of billions. Already, large scale data-centres consume around 1% of global electricity demand, so any efficiency gains in the energy consumption of integrated chips will have significant effects.

As device dimensions reach fundamental physical limits, chip designers are developing new architectures in order to continue to deliver growth in chip performance. These designs require high bandwidth communications across millimetre length scales, currently realised as simple electronic tracks. By replacing these tracks with optical interconnects, system power consumption can be reduced and communications bandwidth improved. The fundamental challenge for any alternative technology is that it must be compatible with current electronics manufacturing, where vast investments have been made over the last decades.

This project will develop an optical interconnect layer that has a link power consumption lower than equivalent electronic lines. The optical layer will be realised as a thin film chip that can be interposed between the silicon device and its packaging, meaning that this process is zero-change with respect to the manufacture of the electronic chips. Recent advances pioneered at the Universities of Strathclyde and Sheffield in ultra-high precision micro-assembly of opto-electronic membrane systems will enable a two stage process that is designed to be compatible with production at scale. Firstly, membrane optical sources, waveguides and detectors will be assembled on a glass chip that incorporates electrical vias. This interposer with integrated optical interconnects will be integrated between the electronic chip and its packaging using micro-assembly processes.

The project is supported by industrial partners Alter Technologies and Fraunhofer UK who will provide resources and expertise in opto-electronic packaging and optical systems engineering. This will ensure new process developments with industrial standards and design rules.

The proposal aligns with EPSRC's ICT and Manufacturing the Future themes and the Photonics for Future Systems priority, addressing specific portfolio areas such as Manufacturing Technologies, Optical Communications, Optical Devices & Subsystems, Optoelectronic Devices & Circuits, Components & Systems.

By the end of the project we will have demonstrated an optical transmission link with energy consumption lower than an equivalent electronic line. This link will be integrated with a commercially available silicon transceiver chip to demonstrate feasibility of developing this technology as a back-end process in the silicon electronics industry.

Key Findings
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Organisation Website: http://www.strath.ac.uk