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Details of Grant 

EPSRC Reference: EP/V002759/1
Title: A new low-complexity paradigm for analogue computation and hardware learning
Principal Investigator: Sporea, Dr RA
Other Investigators:
Researcher Co-Investigators:
Project Partners:
NanoRennes / IETR National Physical Laboratory Sharp Laboratories of Europe Ltd
Silvaco University of Cambridge Yamagata University
Department: ATI Electronics
Organisation: University of Surrey
Scheme: EPSRC Fellowship
Starts: 01 November 2020 Ends: 31 October 2025 Value (£): 1,120,652
EPSRC Research Topic Classifications:
Electronic Devices & Subsys.
EPSRC Industrial Sector Classifications:
Information Technologies Electronics
Related Grants:
Panel History:
Panel DatePanel NameOutcome
03 Aug 2020 EPSRC ICT Prioritisation Panel August 2020 Announced
01 Sep 2020 ICT Fellowship Interviews 1 and 2 September 2020 Announced
Summary on Grant Application Form
The Fellow and his team are seeking to develop a ground-breaking electronic device named the multimodal transistor. Arising from more than a decade of experience in unconventional device design, it allows for entirely new applications such as hardware learning, analog computation and control, while being energy efficient and easy to fabricate.

News headlines in electronic devices usually hail developments in nanoscale billion-transistor chips, yet there are major opportunities for innovation in display screen technologies, in which the requirement of fabricating circuits at low cost over large areas, and not ultimate miniaturization, is prevalent. Existing fabrication facilities are now partly being repurposed for emerging large area electronic (LAE) applications: microfluidics, lab-on-a chip, ubiquitous sensors or wearable electronics. LAE usually contain large arrays of relatively simple circuits with few transistors, as areal performance variations impede the fabrication of complex circuits. Incremental progress in LAE is constantly achieved through processes and equipment improvements, and by using new materials with superior properties, both with large capital investment.

The Fellow proposes a major step in LAE development, a radical new device design: the multimodal transistor (MMT). The MMT enables new ways of designing electronic circuits for efficient analog operations (amplification, data conversion, analog computation), control and feedback, and ultimately, LAE circuits capable of learning (hardware AI), so far impractical with conventional devices and techniques. Functionality is achieved using energy-efficient circuits of minimal complexity, allowing environmentally friendly fabrication at low cost. By greatly expanding the design possibilities, while being entirely compatible with conventional LAE fabrication, MMT circuits extend the usable lifetime of current manufacturing technologies, maximising the return on investment, and can accelerate the uptake of emerging processes such as 2D semiconductors and spatial atomic layer deposition.

The Fellow's team will leverage our long experience in device design and the complementary capabilities of our international partners to design, fabricate and test devices and circuits using vacuum processing and additive manufacturing in conventional and emergent semiconductor systems, supported by state-of-the-art numerical simulation. The team will use their extensive collaborator networks to seed the development of a new electronic design paradigm.

As this is an enabling technology, its applications span fields from disposable medical diagnostics and crop monitoring to autonomous vehicle control, new forms user interfaces and immersive entertainment environments, with substantial long term economical and public benefits for the UK and the world. The implications of the novel functionality, such as hardware AI and autonomy, will be a constantly considered. Stakeholders will be involved in shaping the research through cross-disciplinary workshops, online engagement and science festival participation. The focus on people will further include: continuing a decade-long tradition of training, mentoring and involving school students in the Fellow's research; supporting a strong start to the careers of young researchers involved through mentoring, independence and due to the ground-breaking nature of the work; and incorporating the findings into Surrey's teaching curriculum to increase our graduates' employability.

The Fellowship will accelerate the Fellow's growth as an international technical and thought leader, while retaining valuable skills, intellectual property and know-how in the UK at a time of global uncertainty. A Fellowship is the optimal funding route, allowing full commitment to advancing this trailblazing design paradigm, within a robust structure and collaborative environment which includes world-leading research facilities and support networks.
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Organisation Website: http://www.surrey.ac.uk