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Details of Grant 

EPSRC Reference: EP/V000381/1
Title: CAPcelerate: Capabilities for Heterogeneous Accelerators
Principal Investigator: Jones, Professor TM
Other Investigators:
Researcher Co-Investigators:
Dr AT Markettos
Project Partners:
Department: Computer Science and Technology
Organisation: University of Cambridge
Scheme: Standard Research
Starts: 01 October 2020 Ends: 31 December 2024 Value (£): 1,202,313
EPSRC Research Topic Classifications:
Computer Sys. & Architecture Fundamentals of Computing
EPSRC Industrial Sector Classifications:
No relevance to Underpinning Sectors
Related Grants:
Panel History:
Panel DatePanel NameOutcome
06 Apr 2020 ISCF Digital Security by Design Research Projects Announced
Summary on Grant Application Form
This project seeks to extend the capability hardware security provided by the CHERI computer processor architecture to cover 'accelerators' - hardware designed for speeding up particular specialised tasks. Today accelerators are constructed in a different way to general-purpose processors and increasingly they can be plugged into computers as needed (for instance via a Thunderbolt connection). We wish to architect new ways in which accelerators may communicate with computer systems safely, considering if the accelerator or its software were designed by an untrustworthy agent, or malicious software were loaded on to it. Such protection would provide whole-system security to most current computing systems which depend on accelerators for performant operation. It would also enable users to add accelerators to their system safe in the knowledge that they are not opening themselves up to security vulnerabilities.

As part of this project we will build software and hardware models of accelerators and evaluate potential protections for security and performance, aiming to design efficient and secure protection mechanisms.
Key Findings
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Potential use in non-academic contexts
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Impacts
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Summary
Date Materialised
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Further Information:  
Organisation Website: http://www.cam.ac.uk