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Details of Grant 

EPSRC Reference: EP/S010769/1
Title: FNR - Fundamentals of Negative Capacitance: Towards New Low Power Electronics
Principal Investigator: Zubko, Professor P
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Luxembourg Institute of Science and Tech
Department: Physics and Astronomy
Organisation: UCL
Scheme: Standard Research
Starts: 01 April 2019 Ends: 31 March 2023 Value (£): 464,861
EPSRC Research Topic Classifications:
Electronic Devices & Subsys. Materials Characterisation
Materials Synthesis & Growth
EPSRC Industrial Sector Classifications:
Related Grants:
Panel History:
Panel DatePanel NameOutcome
26 Jul 2018 EPSRC Physical Sciences - July 2018 Announced
Summary on Grant Application Form
Continued miniaturisation of electronic components such as transistors that make up our everyday electronics has been at the heart of the ever-improving performance of these devices. Yet continuing this trend presents ever more complex challenges that require new materials solutions, beyond current silicon technology. One of the big challenges is power consumption and heat dissipation--as transistors get smaller and more of them are packed on a chip, the heat they produce becomes increasingly unmanageable. One possible solution is to replace the gate dielectric, which is used to control the conductivity of the semiconducting channel in the transistor, with a ferroelectric material. Ferroelectrics are materials that spontaneously acquire an electrical polarisation at some temperature and are already widely used in many applications ranging from ultrasound transducers to non-volatile random access memories. Among the many fascinating properties of ferroelectrics, the one that is currently captivating the attention of the semiconductor community is its ability to behave, under certain conditions, as a capacitor with a negative capacitance, i.e. one that charges up in the opposite sense to an ordinary capacitor. Such negative capacitance behaviour can be exploited to amplify the internal potential inside a transistor, allowing it to operate at lower voltages. However, despite an incredible increase in research on negative capacitance devices over the last few years, the fundamental physics of this phenomenon is still very poorly understood. As yet, little is known about the intrinsic mechanism of negative capacitance, its full potential and limitations, how to best characterise this phenomenon experimentally, and how to optimise the materials parameters and device geometries for the best performance. The aim of this project is to address these fundamental questions using a combination of experimental techniques and state-of-the-art theoretical simulations.
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