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Details of Grant 

EPSRC Reference: EP/R012288/1
Title: SCARV: a side-channel hardened RISC-V platform
Principal Investigator: Page, Dr D
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Cerberus Security Laboratories Thales Ltd
Department: Computer Science
Organisation: University of Bristol
Scheme: Standard Research
Starts: 01 February 2018 Ends: 31 January 2023 Value (£): 1,024,324
EPSRC Research Topic Classifications:
Computer Sys. & Architecture Electronic Devices & Subsys.
EPSRC Industrial Sector Classifications:
Information Technologies Electronics
Related Grants:
Panel History:
Panel DatePanel NameOutcome
22 Sep 2017 Research Institute in Hardware Security - Research Projects Announced
Summary on Grant Application Form
RISC-V is an Instruction Set Architecture (ISA) design. An ISA is essentially a specification for the instructions any compatible processor implementation should be able to execute, and the resources those instructions can access; it acts as the interface between the processor implementation (hardware) and programs that execute on it (software). In sharp contrast with proprietary analogues such as the x86 ISA from Intel, RISC-V is an open source design. This means it can be used freely by anyone for any purpose, which, in part, has meant rapid development of a rich support infrastructure around the project: this includes a) vibrant developer and user communities, built around an associated non-profit foundation, b) numerous implementations of the ISA, both in HDL (i.e., a soft core for use on an FPGA platform) and silicon (i.e., physical ICs), and c) ports of programming tool-chains (e.g., GCC and LLVM) and operating systems (e.g., Linux).

Similar openness is a core principle in security-critical contexts, contrasting with the alternative often colloquially termed "security by obscurity". This is particularly true in the field of cryptography, a technology routinely tasked with ensuring secrecy, robustness and provenience of our data (communicated or stored), and the authenticity of parties we interact with: open development of cryptographic standards, designs, and implementations is the modern norm. As a result, RISC-V presents various opportunities when used to execute cryptographic software. The proposed research goals capitalise on these opportunities, in a way designed to address advanced, persistent threats to our digital security, and, by extension, society. Specifically:

1) Since RISC-V can be implemented by anyone, it is possible to develop a core hardened against specific types of attack; the focus will be on the threat of side-channel attacks (which is particularly relevant to embedded use-cases, e.g., IoT). As well as doing so, the proposed research will investigation how detailed information about the implementation can be harnessed to produce more effective security evaluations.

2) Since RISC-V can be adapted by anyone, it is possible to develop various cryptography-specific extensions or variants of the ISA that offer either, for example, higher efficiency. If cryptographic software is more efficient it can also be more secure, because, for example, larger keys or more robust attack countermeasures can be deployed without as significant an impact on latency.

3) Evaluation of side-channel security can be prohibitive in the sense it needs various specific items of equipment. Harnessing a platform based on RISC-V, the proposed research with address this problem by offering a "lab. free" (i.e., cloud-based) acquisition and analysis workflow available to anyone.
Key Findings
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Organisation Website: http://www.bris.ac.uk