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Details of Grant 

EPSRC Reference: EP/L027070/1
Title: SONATAS: Synthetic On-Chip and Off-Chip Optical Network System
Principal Investigator: Zervas, Professor G
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Advanced Micro Devices Inc (AMD) Huber+Suhner (UK) Ltd
Department: Electrical and Electronic Engineering
Organisation: University of Bristol
Scheme: First Grant - Revised 2009
Starts: 31 December 2014 Ends: 30 June 2016 Value (£): 98,216
EPSRC Research Topic Classifications:
Digital Signal Processing Networks & Distributed Systems
Optical Communications
EPSRC Industrial Sector Classifications:
Manufacturing Communications
Healthcare Energy
Information Technologies
Related Grants:
Panel History:
Panel DatePanel NameOutcome
09 Apr 2014 EPSRC ICT Responsive Mode - Apr 2014 Announced
Summary on Grant Application Form
Optical network infrastructure has underpinned the Internet pervading everyone in some way and has stimulated relentless traffic growth. Current network infrastructure is made of stacked layers of function rigid systems. That includes optical switching nodes in conjunction with a set of transmission (i.e. 100Gbps and beyond) and transport (e.g. OTN) systems as well as Layer 2 switches, IP routers, to deliver end-to-end network infrastructure. Such networks are designed and optimised to deliver a fixed set of functionalities for the lifetime of their deployment. Recently there is a shift towards creating a more flexible control and transport by use of software defined network (SDN). SDN however introduces an inbuilt assumption that there is relatively dumb hardware for data switching and forwarding while having relatively intelligent software. This inherently restricts the flexibility of a network environment.

The vision behind this project is to introduce and investigate a radically new and groundbreaking approach to accommodate future infrastructure needs in a more agile, flexible, programmable and evolvable manner down to the hardware level. This will be delivered by open programmable hardware eco-system (photonic and electronic) where the software/hardware programmable devices can be synthesized on-demand to support any and as many function(s) and layers and be re-purposed during their lifetime. Software/Hardware network functions can be interconnected electronically and/or optically to compose and synthesize a system on demand. This is an original and disruptive concept and proposal that defines the Synthetic Node and Network system. It is expected to deliver a breakthrough on Internet and beyond.

The synthesis will consist of interconnection of electronic (e.g. FPGA processing blocks) and photonic (e.g. switching, elastic filtering, amplification, multicasting, etc.) function blocks to compose an fused on-chip off-chip system necessary to perform a particular function and deliver the associated network performance. Such approach eliminates the notion of dimensioning, deploying and provisioning applied on traditional networks designed with function rigid systems. The software-hardware function blocks can be also re-used on any future general-purpose programmable hardware (e.g FPGA/SoC) eliminating disruptive migration lifecycles. This also allows for network users (e.g. operators, service providers) to re-purpose the functions on their physical or virtual infrastructure on demand to suit the network service needs. This inherently redefines the system infrastructure and creates a new research field that fuses electronic and photonic programmability that opens up a new set of opportunities and challenges.

The project will first investigate the formulation of function block behaviour realised both in electronics (i.e. data queuing, framing, protocols) and photonics (i.e. filtering, multiplexing, frequency/space switching). Such function blocks will be interconnected by an network topology (on-chip and off-chip) through the use of synthesis algorithms to compose a complete system. To deliver efficient synthesis, the composition framework and algorithms will consider infrastructure constraints (FPGA timing/space, and optical sub-system characteristics). Techniques will be devised and investigated to deliver isolation between distinct network programmable functions that co-exist on the same opto-electronic hardware substrate.

The project provides direct contribution spanning across multiple EPSRC Priority Areas such as ICT networks and distributed systems as well as optical communications and micro-electronics design. Specifically it addresses the Towards an Intelligent Information Infrastructure (TI3) challenge. So it consequently fits with the EPSRC Working Together priority. It is this context that SONATAS is vital to the development of the future of information society.
Key Findings
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Potential use in non-academic contexts
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Date Materialised
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Organisation Website: http://www.bris.ac.uk