EPSRC logo

Details of Grant 

EPSRC Reference: EP/K015214/1
Title: A higher-order approach to codesign - 27659
Principal Investigator: Ghica, Professor DR
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Department: School of Computer Science
Organisation: University of Birmingham
Scheme: Standard Research
Starts: 17 June 2013 Ends: 16 December 2016 Value (£): 274,300
EPSRC Research Topic Classifications:
Fundamentals of Computing System on Chip
EPSRC Industrial Sector Classifications:
Related Grants:
Panel History:
Panel DatePanel NameOutcome
06 Nov 2012 *ICT* Announced
Summary on Grant Application Form
Current computing architectures are moving increasingly towards

heterogeneity, as physical limitations of scale demand a

bifurcation of optimisation techniques between reducing latency and

increasing throughput. In the past, the amount of heterogeneity in

devices tended to be limited, therefore RTL were largely suitable for for

hardware design. However, recently there has been a surge

of industrial interest in hybrid programmable hardware-software systems.

For example, Xilinx has recently launched the

Zynq platform which combines a multicore ARM processor with programmable

logic. This development thrusts the question

of design for such hybrid systems, requiring different programming

methodologies, into the foreground.

In general, as architectures move away from the conventional CPU and RAM

(von Neumann) model, the task of devising

programming models for them falls mostly with their designers, who are

usually engineers rather than programming

language experts. As a result we are witnessing a flurry of

architecture-specific languages (ASL), reminiscent of the early

days of computation when each computer came with its own operating system,

programming language, etc. Whereas ASLs

are unavoidable, good programming methodology recommends that they should

be used primarily for the development of

system-level infrastructure. The application-level, algorithmic

programming should happen as much as possible in portable,

machine-independent languages. These lessons are very well known in the

programming community and this knowledge

can be profitably used in electronic design. We aim to address this


The challenge of heterogeneous codesign is both quantitative and

qualitative. A program has components that must be

compiled into the FPGA fabric and others to be compiled for the CPU. The

reasons are either efficiency (certain

architectures are better at running certain types or code) or physical

constraints (interactions with other components in a

complex design, availability of IP cores, drivers or libraries). But a

program may also have components which can be

compiled to either architecture or both. A choice must be made and it is

reasonable for this choice to be also motivated by


In this proposal we will combine and unify the way type systems in

higher-level languages specify and solve qualitative

(hard) constraints with quantitative optimisation techniques.

Specifically, we will investigate the optimization of memory

subsystems to support parallel access, by combining knowledge of memory

access patterns from the code, resulting in

highly efficient programmable memory controllers. In addition, we will

optimize the allocation of precision within a combined

hardware/software system in order to achieve an accuracy specification

while taking into account the capability and cost

implications of the programmable hardware and native data types supported

in the software. This combined approach can

work both at the source code level (program transformations motivated by

underlying cost models) and at the synthesisedmachine code and HDL level

(pipelined optimisations, etc). We will use a "game semantic" model,

already successfully

applied to hardware synthesis from higher order languages, to establish

the correctness properties of the type system and

to drive the compilation process.

Key Findings
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Potential use in non-academic contexts
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Description This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Date Materialised
Sectors submitted by the Researcher
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Project URL:  
Further Information:  
Organisation Website: http://www.bham.ac.uk