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Details of Grant 

EPSRC Reference: EP/I033165/1
Title: Novel Sub-Threshold Methodologies for GaN Electronic Devices: A Study of Device Reliability and Degradation Mechanisms
Principal Investigator: Kuball, Professor M
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Fraunhofer Institut (Multiple, Grouped) International Rectifier TriQuint Semiconductor
United Monolithic Semiconductors (UMS)
Department: Physics
Organisation: University of Bristol
Scheme: Standard Research
Starts: 01 May 2011 Ends: 31 October 2015 Value (£): 414,656
EPSRC Research Topic Classifications:
Electronic Devices & Subsys. Power Electronics
EPSRC Industrial Sector Classifications:
Related Grants:
Panel History:
Panel DatePanel NameOutcome
15 Mar 2011 EPSRC ICT Responsive Mode - Mar 2011 Announced
Summary on Grant Application Form
GaN power electronics, in particular, AlGaN/GaN high electron mobility transistors (HEMT) are currently being developed and starting to be applied for power conversion, radar, satellite and communication applications. Switched mode power systems based on this will deliver improved efficiency, hence forming a key enabling technology for the low carbon economy. Although performance of these devices is fully sufficient to enable disruptive changes for many system applications, reliability is presently still in question, not only in the UK and Europe, but also in the USA and Japan. This proposal aims at developing a new electrical methodology to study and understand reliability of GaN based HEMTs, in particular to identify the nature of electronic traps generated during the operation of GaN HEMTs, and which affect their lifetime. The programme is supported by key UK, European and US industries (International Rectifier UK, Fraunhofer Institute IAF Germany, UMS Germany, TriQuint USA), and builds on leading expertise in the field of GaN HEMT reliability developed at the Center for Device Thermography and Reliability (CDTR) in Bristol, established in various research programmes in Bristol funded by EPSRC and the US Office of Naval Research (ONR). The focus of this work will lie in overcoming the challenge that the highly accurate standard Capacitance-Voltage (CV) or Conductance technique for probing electronic traps in semiconductor devices cannot be performed on transistor structures relevant to real applications. This is because these techniques require large transistor structures to have enough capacitance to be measurable. Realistic devices have short gate length with consequently too low a capacitance to be accurately measured at the typical measurement frequency of 1kHz-1MHz, also any damage introduced into a device during device operation is typically in too small an area to be easily detectable using traditional techniques. In contrast, methods which can be applied to small III-V FET devices such as current-DLTS or transconductance dispersion respectively use a non-equilibrium pulse technique which is prone to misinterpretation, or have only given qualitative information to date. A key insight which underpins this proposal is that electronic traps in or near the channel primarily generate dispersion in a device below the pinch off voltage in the sub-threshold regime of operation which will be exploited in this programme. We will develop a dynamic transconductance method for GaN HEMT reliability analysis, suitable for small HEMT devices and insensitive to gate leakage currents. The development of this new electrical methodology which delivers the advantages of the quasi-equilibrium capacitance techniques but in small devices, will allow accurate measurements of degradation induced trap properties to be made for the first time. Noise measurements will complement this novel trap analysis, in additional we will benefit from the pulsed electrical-optical trapping analysis technique we developed in the ONR funded DRIFT programme. The work will advance the understanding of GaN HEMT device degradation during operation, i.e., device reliability, and will keep the UK at the forefront of internationally leading semiconductor device reliability research. The methodologies to be developed will also have direct applicability to the burgeoning worldwide effort in III-V CMOS technology for scaled low-power logic.
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