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Details of Grant 

EPSRC Reference: EP/I012907/1
Title: High permittivity dielectrics on Ge for end of Roadmap application
Principal Investigator: Hall, Professor S
Other Investigators:
Mitrovic, Professor IZ Chalker, Professor PR
Researcher Co-Investigators:
Project Partners:
Department: Electrical Engineering and Electronics
Organisation: University of Liverpool
Scheme: Standard Research
Starts: 01 April 2011 Ends: 31 March 2014 Value (£): 536,891
EPSRC Research Topic Classifications:
Electronic Devices & Subsys.
EPSRC Industrial Sector Classifications:
No relevance to Underpinning Sectors
Related Grants:
EP/I012966/1 EP/I014047/1
Panel History:
Panel DatePanel NameOutcome
13 Oct 2010 ICT Prioritisation Panel (Oct 2010) Announced
Summary on Grant Application Form
The semiconductor industry is now driven largely by applications pull for mass market consumer goods and it is essential that circuit performance is continually improved if the insatiable demand for such products is to be satisfied. The continuing miniaturisation of transistors within CMOS circuits or 'chips' results in degradation of transport properties in the Si-based MOS transistor channels resulting in reduced drive current and hence circuit speed. It is also increasingly difficult to engineer transistors wherein the ultra-short channel (10s of nanometre) is controlled exclusively by the gate electrode; so-called 'short channel effects'. To control this latter effect, increasingly thin gate dielectric is required (circa 2nm) but this leads to excessive leakage curent through the gate through the quantum mechanical tunnelling effect. This gate leakage compromises the operation of the transistor and most importantly, gives rise to very considerable power consumption which reduces battery lifetime in portable products, and also contributes to severe heating of the chip. The use of a dielectric with a higher permittivity (k) allows for a thicker gate oxide with much reduced leakage, whilst maintaining the drive current of the transistor.Germanium semiconductor was used for the very first transistors and possesses excellent transport properties, far superior to those of Si. The successful integration of hafnia based dielectrics for the MOS gate stack, first by Intel, closely followed by other major companies, has been instrumental in installing a new radicalism into the industry. Thus there is now considerable interest incorporating a Ge pMOST and either Ge or a III/V material for the nMOST within CMOS gates. The disadvantage of the lack of a good native oxide for the case of Ge is now mitigated by the availability and proven nature of deposited dielectrics. The combination of a high mobility channel made in Ge, and a reliable hi-k gate dielectric, is highly desirable. The central aim of this project then is to advance the knowledge and underlying science of Ge MOSFETs, crucially in the area of the gate stack. In particular, rare-earth dielectrics on Ge offer the possibility of a 'magic bullet' solution: a fully scaleable gate stack on a high mobility channel, to the end of the CMOS road map dictated by 'Moore's Law.' Hafnia-based gate stacks are at a more advanced stage in the field but require an interfacial layer which calls for further study into the stability of the native oxide (GeO2) and a technological solution for surface passivation. The 'k' can be increased by doping of the hafnia. There is a pressing need to understand the physics underlying the turn-on or threshold voltage of Ge transistors, which is affected by parasitic 'acceptor-like' energy states near the valence band edge and hence find an engineering solution. New measurement techniques need to be developed to assess phenomena peculiar to Ge devices. Furthermore, the reliability has hardly been looked at for Ge oxide stacks. There are certainly a radically different set of issues compared to Si which will have, in turn, an impact on the suitable materials in the gate stack. Interface states near the conduction band edge are thought to be responsible for the low electron mobility which is proving a 'killer' for the nMOST. These technological challenges will be addressed in this project, by a team who have individually and collaboratively, had active participation in dielectrics research over a period of decades. The team cover the subject from atomistic level theory and modelling, through screening of novel materials and chemical precursors, growth and deposition, fabrication, physical and electronic characterisation; to reliability testing. The group members have very strong links into industry and research institutions along this chain of expertise.
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Organisation Website: http://www.liv.ac.uk