Details of Grant 

EPSRC Reference:	EP/H023666/1
Title:	Ferroelectrics for Nanoelectronics (FERN)
Principal Investigator:	O'Neill, Professor A
Other Investigators:	Briddon, Dr P
Researcher Co-Investigators:
Project Partners:	Centre for Process Innovation Limited Intel Corporation Ltd National Semiconductor Neocera Inc NMI (National Microelectronics Inst)
Department:	Electrical, Electronic & Computer Eng
Organisation:	Newcastle University
Scheme:	Standard Research
Starts:	01 June 2010	Ends:	30 November 2013	Value (£):	528,499
EPSRC Research Topic Classifications:	Electronic Devices & Subsys. Materials Characterisation Materials Processing
EPSRC Industrial Sector Classifications:	Electronics
Related Grants:	EP/H023003/1
Panel History:	Panel Date Panel Name Outcome 20 Nov 2009 ICT Prioritisation Panel (Nov 09) Announced
Summary on Grant Application Form
The evolution of silicon technology since the 1960's has focussed on doubling performance and functionality every 18-24 months through miniaturization. Critical dimensions measured in tens of nanometres are now common place and billions of components connected by miles of wiring can be packed onto a wafer no larger than a thumb nail. Today the focus is shifting away from more scaling (called more Moore after the founder of Intel, Gordon Moore) towards increasing functionality through the introduction of mixed technologies on silicon (called more than Moore). This project investigates the incorporation of ultra thin ferroelectric materials into silicon nanoelectronics and two of its many applications.Capacitance is the rate of change of charge with voltage. It is the defining property of capacitors which are necessary in many electronic systems but are relatively large. Ferroelectrics can shrink capacitors by three orders of magnitude, because their electric permittivity is so high. More than that, their capacitance can be made to vary depending on the applied voltage so very small and tunable capacitors can be made, which can find applications in hand held electronics products in order to reduce power consumption. If they could be integrated onto a silicon microchip there would be further space savings. Thin layers are expected to produce even higher capacitance. However there is evidence that capacitance starts to reduce below 50 nm as dead layers are said to form near the interface with electrodes, but this may be an interface effect which can be lessened through engineering. Recently there has been experimental evidence that effective negative capacitance can be seen in ultra-thin ferroelectric films. If such material can be incorporated into a transistor then it would be able to reduce the voltage needed to switch a transistor between its on and off states (the sub-threshold slope). This would transform silicon technology, allowing a new generation of more powerful single core processors. Modern computers have dual or multi-core processors. A single core processor would generate too much heat but is still desirable for many applications. Capacitance places a lower limit on the sub-threshold slope. The consequence is that transistors need a larger applied voltage to be on and/or will leak current and so can never be fully switch off. This leads to increased power loss and heating as more transistors are crammed onto the same area of silicon, which limits component density. Integrating a ferroelectric film with negative capacitance into the gate of a transistor would reduce the overall capacitance and thus the sub-threshold swing. The need to understand and produce high quality ferroelectric ultra-thin films is imperative for each of these applications. Atomic Layer Deposition (ALD) at Newcastle and Pulsed Laser Deposition (PLD) at Imperial College will be used to deposit thin films of the ferroelectric materials barium titanate (BTO) and barium strontium titanate (BST). Both allow deposition thicknesses with atomic level precision. Extensive characterisation is needed to assess quality of these ferroelectric films. First principles computer simulation will be used to gain a better understanding of the films and to direct experiments. The deposition and thermal parameter space will be mapped to identify best ferroelectric properties for given constraints laid down by the silicon fabrication. Transistors will be made incorporating the best ferroelectric films to confirm the reduction in sub-threshold slope. Ferroelectric capacitors integrated onto silicon will be demonstrated, quantifying the capacitance increase per unit area and examining the fabrication constraints needed to maintain high transistor performance. This will also help identify integration issues, which also include equipment contamination and the development of ferroelectric etches.
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