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Details of Grant 

EPSRC Reference: EP/G069352/1
Title: Advanced discretisation strategies for atomistic nano CMOS simulation
Principal Investigator: Bordas, Professor SPA
Other Investigators:
Asenov, Professor A
Researcher Co-Investigators:
Project Partners:
Department: Sch of Engineering
Organisation: Cardiff University
Scheme: Standard Research
Starts: 26 April 2010 Ends: 25 April 2011 Value (£): 103,500
EPSRC Research Topic Classifications:
Electronic Devices & Subsys.
EPSRC Industrial Sector Classifications:
No relevance to Underpinning Sectors
Related Grants:
Panel History:
Panel DatePanel NameOutcome
02 Jun 2009 ICT Prioritisation Panel (June 09) Announced
Summary on Grant Application Form
Vision: The idea of this proof-of-concept research is to investigatehow recent revolutionary advances in computational mechanics can beleveraged to enhance the modelling of nano complementarymetal-oxide-semiconductor (CMOS).The size of the CMOS devices is aggressively being reduced into thedeca-nanometer range (one hundredth of a micron). It isprojected that mass-produced metal-oxide-semiconductor field-effecttransistors (MOSFETs) will reach gate lengths as small as 7 nanometersby 2018 (2003 edition of the International Technology Roadmap forSemiconductors).Modelling and simulation provides deep insight into the operation ofmodern semiconductor devices and circuits, and dramatically reducesthe development costs and time-to-market.Modelling devices at the deca-nanometer scale face significantdifficulties associated with the statistical variability from onetransistor to another introduced by the granularity of matter at thisscale. The Device Modelling Group (Asen Asenov) in the ElectricalEngineering Department at Glasgow University is the world leader inCMOS variability simulation developing unique computational tools tailored tofacilitate the design the next generation of nano-CMOS.While these techniques are very well suited to simulate the effects ofdiscrete dopants, they involve an unnecessary computational cost byrequiring large numbers of grid points when simulating line edge andinterface roughness. It would be greatly beneficial for the practical use simulations of CMOS atthe nano-scale if this computational cost could be reduced.Stephane Bordas, from the Mechanics and Materials Group of the CivilEngineering Department at Glasgow University has developed efficientnumerical techniques which have the potential to significantlydecrease the computational burden through enrichment of the numericalscheme with a priori knowledge about the solution and by allowing theuse of low quality discretisations without sacrificing accuracy.This proof-of-concept research will investigate how the novelnumerical techniques devised in Bordas' group in the context ofmechanics problems can be generalised to increase the accuracy versuscomputational cost ratio in nano-scale CMOS simulators.
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