Details of Grant 

EPSRC Reference:	EP/G032904/1
Title:	Process Variation Aware Synthesis of Nano-CMOS Circuits
Principal Investigator:	Pradhan, Professor D
Other Investigators:	Wilson, Professor P
Researcher Co-Investigators:
Project Partners:
Department:	Computer Science
Organisation:	University of Bristol
Scheme:	Standard Research
Starts:	01 October 2009	Ends:	28 February 2013	Value (£):	281,402
EPSRC Research Topic Classifications:	Electronic Devices & Subsys. Modelling & simul. of IT sys.
EPSRC Industrial Sector Classifications:	Electronics
Related Grants:
Panel History:	Panel Date Panel Name Outcome 01 Dec 2008 ICT Prioritisation Panel (December 2008) Announced
Summary on Grant Application Form
In the context of development of nanoscale CMOS technology, the challenges for design engineers have increased. Design decisions are based on the nominal values of power, and performance decisions are based on the assumption that all the transistors are alike across dies and wafers. However, in reality, when the transistors are quite small, the transistor parameters vary from die to die or even in the same die. In other words, each transistor in a die or wafer is different. The transistor parameter variations may be due to several factors, including changes in dielectric thickness, substrate, polysilicon, and implant impurity levels; surface charge; and lithographic process. Thus, the design decisions based on the nominal models may not be correct because the models are either overestimations or underestimations of actual values; hence, the resultant circuits may not be optimal. Accurate modelling and estimation of all the forms of power and performance accounting process variation, including all leakage components, are crucial for making correct decisions on design for manufacturing. Unfortunately, no comprehensive model or tools exist for accurate estimation during digital system design when the target technology is nanoscale CMOS. Some forms of the power dissipation, such as due to gate-oxide/junction tunneling, have not received much attention. Process-variation-aware modelling of any of the (leakage) current components or delay is significantly challenging when treated at system level. Moreover, no tool exists that can provide power-performance design space exploration when a system is a behavioural hardware description language (HDL). The research proposed in this project intends to develop process variation aware architectural power-delay statistical models and estimator that can be used for fast and accurate estimation of power-performance values of nanoscale-CMOS design alternatives of digital systems expressed as a behavioural HDL.
Key Findings
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Potential use in non-academic contexts
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Impacts
Description This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk Summary Date Materialised
Sectors submitted by the Researcher
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Project URL:
Further Information:
Organisation Website:	http://www.bris.ac.uk