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Details of Grant 

EPSRC Reference: EP/G031576/1
Title: Real-time Numerical Optimization in Reconfigurable Hardware with Application to Model-Predictive Control
Principal Investigator: Constantinides, Professor GA
Other Investigators:
Kerrigan, Professor EC
Researcher Co-Investigators:
Project Partners:
Advanced Micro Devices Inc (AMD) Agility Design Solutions European Space Agency
Department: Electrical and Electronic Engineering
Organisation: Imperial College London
Scheme: Standard Research
Starts: 01 June 2009 Ends: 30 November 2012 Value (£): 527,277
EPSRC Research Topic Classifications:
Modelling & simul. of IT sys. System on Chip
EPSRC Industrial Sector Classifications:
Related Grants:
Panel History:
Panel DatePanel NameOutcome
21 Oct 2008 ICT Prioritsation Panel (Oct 2008) Announced
Summary on Grant Application Form
This proposal is concerned with the hardware acceleration of iterative numerical algorithms, with a focus on model predictive control implementations. Such model predictive controllers typically require the solution of a quadratic progamming problem every sample period. The solution of the quadratic programming problem typically requires several multidimensional Newton optimizations, each of which requires the solution of many systems of linear equations. Thus the lessons learned will be applicable to a wide class of numerical algorithms arising in practical problems within and beyond Control.The main adventurous feature of the approach from the digital electronics perspective is the potential to use Control and Systems theory to inform one of the central design problems in custom reconfigurable computing: efficient silicon utilization through appropriate finite precision number representation. In sequential (single core) computer architecture, questions of numerical precision have, by and large, been answered through the introduction of area costly high-precision IEEE compliant arithmetic units. In modern computing systems, whether FPGA-based or manycore, attention is now turning to how to make the most effective use of the silicon available for computation and, in this context, questions of numerical accuracy requirements are arising once more.The proposed approach forms a radical departure from standard industrial and academic practice in both model predictive control (MPC) and digital electronics. The main adventurous feature of the approach from the end-user perspective is the utilization of reconfigurable hardware devices, namely Field-Programmable Gate Arrays (FPGAs), to implement model predictive controllers operating at high sample rates, allowing MPC to be utilized in application areas where the computational load has been considered too great until now, such as spacecraft, aeroplanes, uninhabited autonomous vehicles, automobile control systems and gas turbines. From the theoretical perspective, the main adventure in Control is in the development of novel formulations that explcitly take advantage of parallel computational architectures.The development of a methodology to tackle this problem will involve highly novel research areas resulting from the application of control theoretic ideas to hardware development, as well as the application of hardware implementation methodologies to control system design. In particular, this proposal is the first to investigate massively parallel real-time numerical optimization on FPGAs, the first to apply control-theoretic techniques to determine appropriate number systems in custom hardware designs, and the first to study the tradeoff between circuit parallelism and numerical accuracy within a closed-loop behavioural context.As a result, this proposal directly falls within the scope of EPSRC's recently signposted Microelectronics Grand Challenge 3 - Moore for Less.
Key Findings
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Potential use in non-academic contexts
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Date Materialised
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Organisation Website: http://www.imperial.ac.uk