Details of Grant 

EPSRC Reference:	EP/F056702/1
Title:	Manufacturable nanoscale architectures for heterojunction solar cells
Principal Investigator:	Friend, Professor Sir R
Other Investigators:	Steiner, Professor U Welland, Professor M Sirringhaus, Professor H Snaith, Professor HJ Greenham, Professor N Huck, Professor W McNeill, Professor CR
Researcher Co-Investigators:
Project Partners:
Department:	Physics
Organisation:	University of Cambridge
Scheme:	Standard Research
Starts:	01 May 2008	Ends:	31 October 2011	Value (£):	1,320,959
EPSRC Research Topic Classifications:	Electronic Devices & Subsys. Materials Processing Materials Synthesis & Growth Solar Technology
EPSRC Industrial Sector Classifications:	Electronics
Related Grants:
Panel History:	Panel Date Panel Name Outcome 25 Feb 2008 Nanotechnology Grand Challenges: Energy Announced
Summary on Grant Application Form
This project will produce manufacturable nanoscale architectures for heterojunction solar cells. Though routed strongly within 'science', the objectives are to achieve engineering solutions to allow the breakthrough needed in this field (target efficiency 10%). Excitonic solar cells based on molecular semiconductors require the presence of a heterojunction between electron and hole-accepting semiconductors in order to separate charges from photogenerated excitons. Large heterojunction interfacial areas are required if all photogenerated excitons are to reach the heterojunction before decaying, and this requires a complex nanoscale architecture. Current methods to achieve this nanostructure and limited and solar cell performance of such devices has stalled. We propose therefore to develop generic routes to separate the control of the nanoscale morphology from the selection of the donor and acceptor semiconductors. This will represent a critical advance in allowing a stable process window, and should allow improved photovoltaic performance through better morphology control and the ability to use semiconductors better matched to the solar spectrum. These routes will be compatible with low temperature processing (this is critical for low-cost manufacturing). The general principle we will use is to separate the processes needed to form the desired nanoscale architecture from the subsequent formation of the active semiconductor-semiconductor heterojunctions at which charge separation is achieved.Central to our approach is the use of 'sacrificial' polymer structures that provide excellent control of nanoscale morphology, and their later replacement with active semiconductors. We will use the controlled nanoscale structures produced using di-block copolymers
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Further Information:
Organisation Website:	http://www.cam.ac.uk