EPSRC logo

Details of Grant 

EPSRC Reference: EP/F033311/1
Title: Semi-insulating Silicon substrates for high frequency integrated circuits
Principal Investigator: de Groot, Professor C
Other Investigators:
Ashburn, Professor P
Researcher Co-Investigators:
Dr K Mallik
Project Partners:
MEMC Electronic Materials SpA Zarlink
Department: Electronics and Computer Science
Organisation: University of Southampton
Scheme: Standard Research
Starts: 01 July 2008 Ends: 31 December 2011 Value (£): 308,697
EPSRC Research Topic Classifications:
Materials Characterisation Materials Synthesis & Growth
EPSRC Industrial Sector Classifications:
Related Grants:
Panel History:
Panel DatePanel NameOutcome
18 Mar 2008 Materials Prioritisation Panel Meeting (March 08) Announced
Summary on Grant Application Form
Semi-insulating silicon substrates would be very attractive as handle wafers in Silicon On Insulator (SOI) technologies because they would provide very low-absorption substrates for RF and monolithic microwave integrated circuits. Two of the investigators have previously theoretically analysed the effect of different deep level impurities on silicon resistivity and shown that a resistivity of nearly 100kOhm.cm should be achievable by dopant compensation. This theoretical work has been supported by our recently published experimental feasibility study that has delivered a very promising resistivity value of 12kohm.cm using Mn as the deep level impurity. This proposal aims to study the science and engineering of high resistivity silicon substrates for high frequency integrated circuits. The team encompasses expertise on the materials science of deep level impurities (University of Oxford), on the physics and technology of high frequency silicon devices (University of Southampton), on silicon wafer growth (MEMC) and on the design and fabrication of high frequency integrated circuits (Zarlink). The project aims to better understand the diffusion and doping vs resistivity relations of appropriate deep level impurities (including Mn), and hence to maximise the resistivity of the silicon handle wafer. Contamination issues arising from the deep level impurities will be addressed by investigating diffusion barriers and also by developing a back-end processing approach that takes advantage of the high diffusivity of some deep level impurities. The recent incorporation of Cu metallization into back-end silicon production processes suggests that other deep level impurities would not be seen by industry as a major contamination issue in back-end processing. Finally, SOI wafers will be fabricated on semi-insulating silicon substrates and detailed high frequency characterisation carried out.
Key Findings
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Potential use in non-academic contexts
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Description This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Date Materialised
Sectors submitted by the Researcher
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Project URL:  
Further Information:  
Organisation Website: http://www.soton.ac.uk