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Details of Grant 

EPSRC Reference: EP/E062164/1
Title: Energy Efficient Networks-on-Chip for Dynamically Reconfigurable Computing Platforms.
Principal Investigator: Nunez-Yanez, Dr J
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Advanced Micro Devices Inc (AMD) Silistix Ltd STMicroelectronics
Department: Electrical and Electronic Engineering
Organisation: University of Bristol
Scheme: Standard Research
Starts: 12 December 2007 Ends: 11 December 2010 Value (£): 282,919
EPSRC Research Topic Classifications:
System on Chip
EPSRC Industrial Sector Classifications:
Electronics
Related Grants:
EP/E06065X/1
Panel History:  
Summary on Grant Application Form
The purpose of this work is to investigate an on-chip network fabric that will enable future reconfigurable computing systems integrating tens or hundreds of processing tiles implementing embedded microprocessors, intellectual property cores, reconfigurable fabrics, dedicated local memories and DSP functionality. The reconfigurable NoC fabric will direct the effective communication and exchange of data among the multiple processing tiles and enable fault-tolerance and very high communication bandwidths with low-latency and low energy consumption. The processing tiles will morph their functionality and operation point based on the application demands.
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Summary
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Project URL:  
Further Information:  
Organisation Website: http://www.bris.ac.uk