Details of Grant 

EPSRC Reference:	EP/D070236/1
Title:	Modelling of Carrier Transport in Ultra Thin Body Transistors
Principal Investigator:	Kalna, Professor K
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Department:	Electronics and Electrical Engineering
Organisation:	University of Glasgow
Scheme:	Advanced Fellowship
Starts:	01 March 2007	Ends:	28 February 2010	Value (£):	525,161
EPSRC Research Topic Classifications:	Electronic Devices & Subsys.
EPSRC Industrial Sector Classifications:	Electronics
Related Grants:
Panel History:	Panel Date Panel Name Outcome 25 Apr 2006 ICT Fellowships 2006 - Interview Panel Deferred 21 Mar 2006 ICT Fellowships 2006 - Sift Panel Deferred
Summary on Grant Application Form
Aggressive scaling of the conventional metal-oxide-semiconductor field effect transistors is required by the International Technology Roadmap for Semiconductors as conventional devices will hit a limit beyond the 45 nm technology node. Novel, ultra-thin body transistors must be introduced into production in order to sustain the expected increase in device performance. Moreover, both the Silicon device body and the SiO2 dielectric have to be replaced with a higher mobility semiconductor and higher dielectric constant materials.The proposed fellowship research aims to develop a 'state-of-art' Monte Carlo device simulator which is capable of accurately modelling the low-dimensional properties of ultra-thin body transistors. The simulator will be employed to optimise the ultra-thin body architecture, to benchmark the prospective high mobility materials, and to investigate the impact of high-K dielectrics on channel mobility. It will also focus on the exploitation of different material crystal orientations in the channel. The accompanying research grant proposal aims to establish a new Monte Carlo simulation tool and enhancing the collaborators' Non-Equilibrium Green Functions simulator employed in the investigation of nanowire transistors.
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Organisation Website:	http://www.gla.ac.uk