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Details of Grant 

EPSRC Reference: EP/C547861/1
Title: Automatic Test Pattern Generation and Scan Insertion for Asynchronous Circuits
Principal Investigator: Efthymiou, Dr A
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Department: Sch of Informatics
Organisation: University of Edinburgh
Scheme: First Grant Scheme Pre-FEC
Starts: 01 December 2005 Ends: 30 November 2008 Value (£): 94,379
EPSRC Research Topic Classifications:
VLSI Design
EPSRC Industrial Sector Classifications:
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Panel History:  
Summary on Grant Application Form
The fast evolution in semiconductor technology brings along not only speed and cost benefits, but also hard challenges for circuit and system designers. One of the major challenges is how to distribute the 'clock' signal, a timing reference signal broadcast to the whole chip that dictates when system state is updated and synchronises all information exchanges. An extreme solution is to remove the clock altogether, leading to the asynchronous design style. While there are currently very few fully-asynchronous systems, the semiconductor industry roadmap predicts that, in the near future, conventional integrated circuits will be employing some asynchronous circuits mostly for the communication between blocks that have independent clocks.Unfortunately, current solutions for post-fabrication testing of asynchronous circuits are not as mature as those for synchronous circuits. This means that it is hard to tell if an asynchronous circuit, or the asynchronous part of a future system, has been fabricated without any faults. As commercial chips must have a fault-coverage of nearly 100%, it is clear that the testability of asynchronous circuits must be improved.The overall aim of this project is to develop a methodology for testing asynchronous circuits and implement a tool that will be able to convert a given circuit into a testable equivalent and produce the sequence of test-vectors required for actually performing the test.A commonly used method in synchronous design is to add extra circuits (scan-latches) that can aid the testing task. A direct application of the method to asynchronous circuits has already been proposed and it can successfully produce testable circuits, albeit at an extremely high cost, because the number of added scan-latches is enormous. This project will investigate methods for adding the minimum number of scan-latches that will produce a fully testable circuit and explore the trade-offs between cost and test coverage for asynchronous circuits.By reducing the number of added scan-latches, the task of test-pattern generation becomes harder as the order in which the patterns are applied becomes critical. Thus, the second major objective of the project is to produce a tool that generates test patterns for the asynchronous circuits. Existing tools are designed assuming synchronous operation and thus produce test patterns with a very low fault coverage for asynchronous circuits.The research has the potential to produce practical tools that will fill in a gap in the existing Electronic Design Automation (EDA) tool range. It is worth noting that the UK is home to a relatively high percentage of the world's asynchronous design community, in both academia and industry, which will directly benefit from this research. Moreover, as testing is considered the Achilles' heel of the asynchronous technology, a successful outcome will help to expand the adoption of this design style to a wider design community
Key Findings
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