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Details of Grant 

EPSRC Reference: EP/C509625/1
Title: Parallel Enumeration: Applications, Tools and Architectures
Principal Investigator: Luk, Professor W
Other Investigators:
Mencer, Dr OP
Researcher Co-Investigators:
Project Partners:
Department: Computing
Organisation: Imperial College London
Scheme: Standard Research (Pre-FEC)
Starts: 01 April 2005 Ends: 30 September 2008 Value (£): 298,291
EPSRC Research Topic Classifications:
Parallel Computing
EPSRC Industrial Sector Classifications:
No relevance to Underpinning Sectors
Related Grants:
Panel History:  
Summary on Grant Application Form
This proposal concerns a novel method for design optimisation of reconfigurable hardware by enumerating in parallel all circuits of size N, where N is a small constant which improves with technology. The project will study the range of applications that can benefit from the generalisation of this method, as well as tools and architectures that support parallel enumeration in reconfigurable hardware and other technologies. If successful, the research will enable design automation of optimal hardware designs for arithmetic and other applications, as well as yielding theoretical insights about analytical properties of such designs. In addition to new designs composed of building blocks which are found by enumeration to be optimal according to usergiven criteria, the ramifications of the proposed approach may help popularise new generations of computers optimised for parallel enumeration. These computers would be radically different from those in use today, which are mostly based on general-purpose microprocessors.
Key Findings
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Potential use in non-academic contexts
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Impacts
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Summary
Date Materialised
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Project URL: http://cc.doc.ic.ac.uk/cip.html
Further Information:  
Organisation Website: http://www.imperial.ac.uk