| EPSRC Reference: |
EP/I004157/1 |
| Title: |
Breaking the Copper Bottleneck: Computer Architecture and Power Implications of Photonic Interconnect |
| Principal Investigator: |
Watts, Dr PM |
| Other Investigators: |
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| Researcher Co-Investigators: |
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| Project Partners: |
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| Department: |
Computer Science and Technology |
| Organisation: |
University of Cambridge |
| Scheme: |
Career Acceleration Fellowship |
| Starts: |
01 October 2010 |
Ends: |
01 June 2011 |
Value (£): |
647,713
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| EPSRC Research Topic Classifications: |
| Optical Communications |
System on Chip |
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| EPSRC Industrial Sector Classifications: |
| No relevance to Underpinning Sectors |
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| Related Grants: |
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| Panel History: |
| Panel Date | Panel Name | Outcome |
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09 Jun 2010
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EPSRC Fellowships 2010 Interview Panel F
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Announced
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Summary on Grant Application Form |
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The provision of future services in the digital economy is reliant on achieving more power efficient computers. Recent bandwidth improvements in electronic interconnects have only been achieved at the expense of dramatic increases in latency and power consumption [19]. Photonic technologies appear essential to make chip-to-chip communication sustainable for ever-higher data rates due to inherently lower power operation. Recent advances in silicon photonics, photonic printed circuit boards (PCB) and 3D integration technologies indicate great promise for short distance photonics. However, given the radical changes in computer design brought about by chip multiprocessors (CMP) and the fundamental differences between electronic and photonic communications, the design implications for complete computer systems are not clear. The proposed research will study the implications of upcoming photonic technologies on the power consumption and architecture of large computer systems such as high performance computers and data centres. The uniqueness of the proposal is its method and the holistic results that it should produce. I will start with a firm scientific foundation based on characterisation of emerging photonic devices leading to models of existing and predicted future components. FPGA-based emulation will enable investigation of complete multi-chip, multi-core computer systems and interconnect running at around 1/100th of real time. The outcome will be the knowledge to build large computer systems optimised for minimum power consumption. This multidisciplinary research therefore underpins several EPSRC themes: digital economy, next-generation healthcare and energy efficiency as well as responding to the EPSRC signposted Moore-for-Less microelectronic grand challenge.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
https://research.ee.ucl.ac.uk/ong/group-research/photonicinter |
| Further Information: |
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| Organisation Website: |
http://www.cam.ac.uk |