| EPSRC Reference: |
EP/G038961/1 |
| Title: |
Silicon Resonant Tunnelling Diodes and Circuits |
| Principal Investigator: |
Paul, Professor DJ |
| Other Investigators: |
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| Researcher Co-Investigators: |
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| Project Partners: |
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| Department: |
Electronics and Electrical Engineering |
| Organisation: |
University of Glasgow |
| Scheme: |
Standard Research |
| Starts: |
03 August 2009 |
Ends: |
02 August 2012 |
Value (£): |
451,261
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| EPSRC Research Topic Classifications: |
| Electronic Devices & Subsys. |
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| EPSRC Industrial Sector Classifications: |
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| Related Grants: |
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| Panel History: |
| Panel Date | Panel Name | Outcome |
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29 Jan 2009
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ICT Prioritisation Panel (January 2009)
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Announced
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Summary on Grant Application Form |
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Resonant tunnelling diodes (RTDs) are one of the few quantum device technologies which has made production with superior performance compared to rival devices and circuits. All such circuits have been in III-V technology while over 98% of microelectronic sales are silicon devices. Previous work at Cambridge has demonstrated III-V type performance from Si/SiGe RTDs. This proposal is to develop and demonstrate basic circuits using Si/SiGe RTDs combined with strained-Si MOSFETs, a key step required if such technology is to make the leap to production. One application will be investigated as a demonstrator, that of tunnelling static random access memory (TSRAM). The TSRAM has the ability to be integrated with future CMOS microprocessors using strained-Si technology, hence the inclusion in the International Technology Roadmap for Semiconductors (ITRS) of RTD technology. In particular the TSRAM potentially offers 7 orders of magnitude improvement in CMOS SRAM standby power dissipation, now one of the most important parameters in the future scaling of CMOS microprocessors. We also propose to develop existing outreach teaching resources on Moore's law, scaling and post Moore devices to encourage children into science and the U.K. semiconductor industry linked to the proposed research.The work we propose is also aligned with the EPSRC Signposted Grand Challenges in Silicon Technology as set out by the U.K. EPSRC Silicon Futures network (GR/T07879). This particular proposal to some degree straddles all the Technology Grand Challenges but the change of device architecture to RTDs with ~2 nm critical dimensions is most strongly aligned to the G1: Novel Devices and Processes Using Silicon Based Technology. This proposal will develop and validate quantum device models of RTDs (G2.2) and use numerous characterisation techniques at the nm scale (G3). The RTD technology is using SiGe and so we are addressing G4: New Materials Systems for Silicon Based Technologies. As standby power dissipation is also reduced by 7 orders of magnitude compared to SRAM, this is also aligned with the G7 Eco-silicon Grand Challenge and the many potential applications for a successful technology especially with DAC and ADC circuits has strong associations with the G6 Silicon for Life Grand Challenge.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.gla.ac.uk |