Details of Grant 

EPSRC Reference:	EP/F030991/1
Title:	Synthesis and Optimisation of Designs Based on Novel Canonical Algebraic Structures
Principal Investigator:	Pradhan, Professor D
Other Investigators:	Zwolinski, Professor M
Researcher Co-Investigators:
Project Partners:
Department:	Computer Science
Organisation:	University of Bristol
Scheme:	Standard Research
Starts:	01 October 2008	Ends:	30 November 2011	Value (£):	224,575
EPSRC Research Topic Classifications:	System on Chip VLSI Design
EPSRC Industrial Sector Classifications:	Electronics
Related Grants:
Panel History:	Panel Date Panel Name Outcome 24 Jan 2008 ICT Prioritisation Panel (Technology) Announced
Summary on Grant Application Form
Behavioral synthesis, an important part of Electronic System Level (ESL)design, provides the most effective means to optimize the design by allowingthe designer to concentrate on the highest level of design abstraction, namely behavioral and algorithmic levels. Behavioral synthesis has unquestionably the greatest impact on the quality of complex Integrated Circuits (ICs) and systems on chip (SoC) designed with CAD tools. Despite many advances in behavioral synthesis over the past two decades, existing synthesis systems are still ineffective in translating the initial design specification into hardware.In particular, existing tools rely on a single, fixed data flow graph (DFG), extracted from the design specification, and mapped onto hardware.This research proposes a systematic approach to behavioral synthesis based on functional (rather than structural) representation of the computation. In particular, a new method is proposed to perform efficient factorization and decomposition for polynomial expressions derived from algorithmic design descriptions using two novel, canonical algebraic structures:1) Taylor Expansion Diagram (TED), and2) Galois Field Decision Diagrams (GPDD).As canonical representations, these structures can capture an entire class of structural solutions, rather than a single DFG obtainable with current methods. Through a set of novel functional decomposition procedures proposed in this research, the initial functional representation can be converted into a set of structural representations (data flow graphs, DFG), from which an optimum one can be chosen for a particular design objective, such as thecircuit area, latency, power, or performance, leading to efficient hardware implementations.The proposed method will equip the designers with a tool to perform efficient exploration of architectural solutions, without a need to rewrite and re-synthesize the original specification in search for the best solution.
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Organisation Website:	http://www.bris.ac.uk