Details of Grant 

EPSRC Reference:	EP/D068843/1
Title:	EDA tools for strained Si CMOS cell libraries with variability models
Principal Investigator:	Russell, Dr G
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Department:	Electrical, Electronic & Computer Eng
Organisation:	Newcastle University
Scheme:	First Grant Scheme
Starts:	15 January 2007	Ends:	14 March 2009	Value (£):	159,357
EPSRC Research Topic Classifications:	System on Chip VLSI Design
EPSRC Industrial Sector Classifications:	Electronics
Related Grants:
Panel History:
Summary on Grant Application Form
The world market for semiconductors is counted in billions of dollars per year in which 80% of it is dominated by complementary metal oxide semiconductor (CMOS) and interestingly, Si devices account for 97% of all microelectronics. Gradual miniaturization has been the driving methodology for the steady increament of density of transistors in a chip. The industry is projected to be 25 times the present size after 2020 where one year's growth would be larger than today's entire industry. The frequent shrinking of CMOS devices is the key for this growth and it is likely to be continued as long as the industry grows at a significantly faster rate. However, the Gradual miniaturization methodology is being challenged by the device and material physics. To meet the challenge, research began to look for alternatives. One of such an alternatives is the replacement of Si channel in MOS devices by strained Si. The strained Si channel can deliver a very high level of performance without aggressive scaling maintaining its compatibility with the conventional CMOS process. Strain engineering in Si is a crucial feature for future CMOS technology and its benefit in CMOS devices is largely additive to the impact of possible scaling. Since last decade, performance enhancement in strained Si over its Si counterpart has progressed consistently. A thick layer of SiGe grown on a bulk Si substrate forms the virtual substrate (VS). When a thin film of Si is subsequently grown on top of the VS, it is under tensile strain. Introduction of strain in Si channel improves its carrier transport property resulting to high speed devices. However, it has not yet been possible for the design community to exploit the device level performance improvement in strained Si. The enormous potential of strained Si devices can only be extracted fully if it is used at different levels of application oriented logic circuits/blocks. This requires developing front end Electronic Design Automation (EDA) tools with strained Si CMOS devices as the basic units. No such cell libraries or EDA tools are available in academia or industry, and hence, a research program is urgently needed to bridge this gap between the technology and design community. Moreover, the variations in MOSFET parameters have always been a challenge for circuit designers since these variations cause uncertainty in I-V curves, power dissipation, timing analysis, and even leading failure in circuits. In strained Si technology, variability will be even greater than conventional Si due to the higher level of material and device level variability such as higher defects and traps, surface roughness and Ge concentrations. Thus, research aimed at modelling and characterising variations at process, device and circuit levels is also needed. This research proposal addresses the world's first demonstration of strained Si/SiGe based cell libraries for front end EDA tools. This also incorporates process and device level variability in the design. The research proposal will bridge the gap between technology and design community and will provide opportunity to the design community to develop strained Si based VLSI circuits helping to expedite the implementation of strained Si technology into production.
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