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Details of Grant 

EPSRC Reference: EP/G037809/1
Title: VERification-Driven Asynchronous Design (VERDAD)
Principal Investigator: Khomenko, Dr V
Other Investigators:
Yakovlev, Professor A Koutny, Professor M
Researcher Co-Investigators:
Project Partners:
ARM Ltd Elastix Corporation
Department: Computing Sciences
Organisation: Newcastle University
Scheme: Standard Research
Starts: 01 August 2009 Ends: 31 October 2012 Value (£): 412,143
EPSRC Research Topic Classifications:
VLSI Design
EPSRC Industrial Sector Classifications:
Electronics
Related Grants:
EP/G02930X/1
Panel History:
Panel DatePanel NameOutcome
01 Dec 2008 ICT Prioritisation Panel (December 2008) Announced
Summary on Grant Application Form
This project redefines conventional asynchronous VLSI tool flows, by incorporating verification into the heart of the design process. Assertion-based verification is used to drive the synthesis procedure by analysing the behaviour of circuits to prove properties which may be exploited for optimisation. Using verification as part of the synthesis procedure represents a major paradigm shift from existing approaches where the validity of optimisations is determined statically and verification is performed after synthesis. Combining synthesis and verification will provide practical and theoretical advances in both areas extending beyond the focus of the project domain. Results of the project will be disseminated into the VLSI community in the form of tutorials and workshops with the aim of promoting asynchronous circuits as an effective solution to the problem of process variation.
Key Findings
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Potential use in non-academic contexts
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Impacts
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Summary
Date Materialised
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Project URL: http://homepages.cs.ncl.ac.uk/victor.khomenko/projects/verdad.html
Further Information:  
Organisation Website: http://www.ncl.ac.uk